1. Field of the Invention
The present invention relates to a clock synchronous type semiconductor device that accepts input signals inputted from the exterior in synchronization with a clock signal.
2. Description of the Related Art
Generally, a semiconductor device such as an integrated circuit, etc., is roughly divided into a logic LSI such as a microcomputer, etc., and a memory LSI such as a DRAM (Dynamic Random Access Memory), etc. The microcomputer has been publicly known as a clock synchronous type semiconductor device. On the other hand, recently, a clock synchronous type has been developed as a synchronous DRAM in the memory LSI.
The synchronous DRAM operates an interface circuit at a high rate in synchronization with an external clock signal inputted from the exterior, and enables writing and reading of data at a high rate. For example, a synchronous DRAM, the maximum operating frequency of which is 100 MHz or more, has been developed.
FIG. 1 shows an example of configuration of an input interface unit in this type of semiconductor device. The input interface unit 1 is provided with a plurality of input signal accepting circuits 3.
The respective input signal accepting circuits 3 accept an external clock signal CLK and an input signal Din (a) (or Din (b)). The input signal accepting units 3 output internal signals Doutz (a), Doutx (a) (or Doutz (b), Doutx (b)) to an internal circuit 5. Also, the internal signal Doutz is an in-phase signal of the input signal Din, and the internal signal Doutx is an antiphase signal of the input signal Din.
The above-described input signal accepting circuits 3 accepts an input signal Din in synchronization with the external clock signal CLK and output the accepted signal into the internal circuit 5 as internal signals Doutz and Doutx.
FIG. 2 shows an example of acceptance timing of an input signal Din in the input interface unit 1 shown in FIG. 1. In this example, the inputting period of the input signal Din is defined in terms of setup time and hold time with respect to rise of the external clock signal CLK.
The setup time tDS is a specification of the minimum time necessary to confirm the input signal Din prior to a rise of the external clock signal CLK, and the hold time tDH is a specification of the minimum time necessary to hold the input signal Din after a rise of the external clock signal CLK.
By inputting an input signal Din in compliance with the above-described timing specification, the input signal Din is accepted by the rise of the clock signal CLK to generate internal signals Doutz and Doutx.
The setup time tDS and hold time tDH are determined so that the input signal Din can be accepted without fail under the worst conditions, taking into consideration the characteristic fluctuations among semiconductor devices, which are produced in a semiconductor fabrication process, and temperature and/or supply voltage to operate the semiconductor devices.
However, it is necessary that users who have this type of a semiconductor device mounted in a system equipment establish an input signal Din, which is inputted into the semiconductor device, prior to the setup time tDS, and designs the timing in the system equipment to hold it longer than the hold time tDH, as described above.
The system equipment needs a circuit to satisfy the setup time tDS and a circuit to satisfy the hold time tDH, respectively, in order to generate input signals Din, so the circuit configuration of the system equipment has been increasing in scale and has been becoming more and more complicated.
In the case of a semiconductor device whose operating frequency exceeds 100 MHz, generally, the cycle of the external clock signal CLK becomes 10 ns or less. Resultantly, the allowance in the timing design at the system equipment is reduced, and it was difficult to generate input signals Din on the basis of the above-described timing specification.
In particular, in order to secure the setup time tDS of an input signal Din, a rise or a fall of an eternal clock signal CLK one clock cycle beforehand needs to be used, wherein the timing design was very difficult where the cycle of the external clock signal CLK is short.
Therefore, the inventors considered outputting an input signal Din from the system equipment as soon as the external clock signal has done transition, generating a clock signal delayed by a predetermined time with the external clock signal CLK in the above-described input interface unit 1, and accepting an input signal Din in synchronization with the clock signal.
FIG. 3 shows a configuration of an input interface unit 1 that has been considered by the inventors. The input interface unit 1 has the above-described input signal accepting circuits 3 and an inverter 7.
The inverter 7 inputs the external clock signal CLK, and outputs an inverted clock signal /CLK of the external clock signal CLK. The input signal accepting circuits 3 inputs the inverted clock signal /CLK. The other configuration is identical to that shown in FIG. 1.
FIG. 4 shows timing for accepting input signals Din in the input interface unit 1 shown in FIG. 3.
The input signal Din is accepted at a rise (=a fall of the external clock signal CLK) of the inverted clock signal /CLK. In this case, the inputting period of the input signal Din is a specification of the setup time tDS1 and hold time tDH1 with respect to the rise of the inverted clock signal /CLK.
Therefore, when the inputting period of the input signal Din can make the time tDS from the rise of the external clock signal CLK to the establishment of data smaller than a xc2xd cycle of the external clock signal CLK, only the hold time tDH with respect to the rise of the external clock signal CLK need be satisfied.
Resultantly, in the system equipment, users only has to design the timing so that an input signal Din simultaneously generates with the rise of an external clock signal CLK or after the rise thereof, and so that the rise it is held for only the hold time tDH. That is, designing of timings can be facilitated.
FIG. 5 shows the configuration of another input interface unit 1 considered by the inventors. The input interface unit 1 has the above-described input signal accepting circuits 3 and a delay circuit 9.
The delay circuit 9 receives the external clock signal CLK, and outputs a delay clock signal DCLK delayed by a predetermined time to the external clock signal CLK. The respective input signal accepting circuits 3 receives the delay clock signal DCLK. The other configuration thereof is identical to that shown in FIG. 1.
The delay circuit 9 is composed of, for example, a capacitor and a resistor and has a predetermined time constant.
FIG. 6 shows the accepting timing of an input signal Din in the input interface unit 1 shown in FIG. 5.
The input signal Din is accepted at the rise of the delay clock signal DCLK delayed by delay time xe2x80x9cDelayxe2x80x9d from the rise of the external clock signal CLK. In this, the inputting period of the input signal Din is a specification of the setup time tDS2 and hold time tDH2 with respect to the rise of the delay clock signal DCLK.
Accordingly, when the time tDS from the rise of an external clock signal CLK to the decision of data can be made shorter than the delay time xe2x80x9cDelayxe2x80x9d, the inputting period of an input signal Din only needs to satisfy the hold time tDH of the rise of the external clock signal CLK.
Therefore, in the system equipment, users only need to design the timing so that generating input signal Din simultaneously with the rise of an external clock signal CLK or after the rise thereof as in the input interface unit 1 shown in FIG. 3, and hold the rise of the input signal Din for only the hold time tDH. That is, designing timings can be facilitated.
The considerations made by the inventors are not publicly known so far.
However, in the input interface unit 1 having an inverter 7 shown in FIG. 3, an input signal Din is accepted by using an inverted clock signal /CLK obtained by inverting the external clock signal CLK. Therefore, the timing at which internal signals Doutz and Doutx outputted to the internal circuit 5 delays by almost the half of a clock from the timing of the rise of the external clock signal CLK.
For example, in the case where the input interface unit 1 is applied to an accepting part of address signals and data signals in a clock synchronous type memory LSI such as a synchronous DRAM, etc., the access time such as writing time and reading time delays by one half of a clock.
There is a problem in that, although the delay scarcely influences the access time when the frequency of an external clock signal CLK is high, the influence upon the access time is made large as the frequency of the external clock signal CLK, is lowered.
That is, the access time of a memory LSI to which the input interface unit 1 is applied becomes roughly equivalent to the sum of the time required from the selection of a memory cell of a designated address to the output of the selected memory cell to the exterior and the time of one half of a clock of the external clock signal CLK. Although the former time is almost constant without depending upon the frequency of the external clock signal CLK, the latter time may be lengthened as the frequency of the external clock signal CLK is lowered. Therefore, the longer the cycle of the external clock signal CLK becomes (the lower the frequency becomes), the ratio of one half of a clock of the external clock signal CLK to the access time increases, and the influence thereof upon the access time may be increased.
On the other hand, the input interface unit having a delay circuit 9 shown in FIG. 5 accepts an input signal Din, using a delay clock signal DCLK in which the external clock signal CLK is delayed.
The delay time xe2x80x9cDelayxe2x80x9d of the delay circuit 9 may fluctuate, due to the characteristic fluctuations among semiconductor devices which are produced in a semiconductor fabrication process, temperature and/or supply voltage when operating the semiconductor device. The fluctuation does not depend on the frequency of the external clock signal CLK.
The higher the frequency of the external clock signal CLK, the larger the influence due to fluctuations of the delay time xe2x80x9cDelayxe2x80x9d. In detail, for example, in the case where the frequency of the external clock signal CLK is 125 MHz (clock cycle is 8 ns) where the delay time xe2x80x9cDelayxe2x80x9d of the delay circuit 9 fluctuates in a range of 2 ns through 7 ns, the allowance between the maximum value of the delay time xe2x80x9cDelayxe2x80x9d and the clock cycle is only 1 ns, wherein it becomes difficult to design the internal timing of a semiconductor device.
The above-described malfunction occurs when producing a semiconductor device.
There are two kinds of production processes in the semiconductor devices, one of which is a single wafer process in which a wafer in which a plurality of semiconductor devices are formed by being processed one by one, and the other of which is a batch process in which a plurality of wafers are simultaneously processed. The single wafer process is, for example, a photolithography process, and the batch process is, for example, a heat treatment process.
Generally, in the single wafer process, characteristic fluctuation is liable to occur among semiconductor devices in the same wafer, and in the batch process, characteristic fluctuation is liable to occur in different wafers.
As such fluctuations overlap through a plurality of production processes, the fluctuation of the maximum operating frequency of produced semiconductor devices is subjected to a mountain-like distribution having a peak at the middle, as shown in FIG. 7.
The semiconductor devices are classified into three types, the fastest type, highspeed type and standard type, for example, depending on the maximum operating frequency, through a probe test in the wafer state and a selection test after assembly is completed.
At this time, in the case where the input interface unit 1 having an inverter 7 shown in FIG. 3 is applied to a semiconductor device, influence on the access time is increased in the standard type. The semiconductor devices are handled as defective units where the access time thereof exceeds a predetermined time.
In the case where the input interface unit 1 having a delay circuit 9 shown in FIG. 5 is applied to a semiconductor device, influence due to fluctuations of the delay time xe2x80x9cDelayxe2x80x9d is increased in the fastest type. Semiconductor devices are handled as defective units where internal signals Doutz and Doutx cannot be accepted by the internal circuit 5.
As a result, an expected yield cannot be obtained, and the production cost of semiconductor devices is remarkably increased.
It is therefore an object of the invention to provide a semiconductor device that is capable of receiving input signals without fail regardless of the frequency of an external clock signal.
It is another object of the invention to provide a semiconductor device in which the timing of an internal clock signal, which accepts an input signal, is set when the semiconductor device under operation.
It is still another object of the invention to provide a semiconductor device in which the timing of an internal clock signal, which accepts an input signal, is set in a semiconductor fabrication process.
It is yet another object of the invention to provide a semiconductor device in which the timing of an internal clock signal, which accepts an input signal, is automatically set according to the frequency of the external clock signal.
According to one of the aspects of the semiconductor device of the invention, a clock timing selecting unit outputs a predetermined clock selecting signal. A clock generating unit receives a clock selecting signal and an external clock signal and generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal. The input signal receiving unit receives an input signal in synchronization with the clock signal outputted from the clock generating unit. Therefore, the input signal receiving unit is capable of receiving an input signal (address signal, data signal, etc.,) by means of a clock signal having the optimum timing in response to the frequency, etc., of the external clock signal used. That is, it is possible to accept the input signal without fail regardless of the frequency of the external clock signal.
According to another aspect of the semiconductor device of the invention, a clock generating unit is provided with a plurality of internal clock generators, and the respective internal clock generators generate internal clock signals whose phases are inverted compared to that of the external clock signal, or which are delayed from the external clock signal by a predetermined time. The input signal receiving unit receives an input signal using the selected internal clock signal. Therefore, the input signal receiving unit is capable of receiving an input signal even in the case where the input signal is inputted simultaneously with the edge timing of an external clock signal. Resultantly, it becomes possible to relieve the specified input timing of input signals, wherein the timing design of a system equipment on which the present semiconductor device is mounted can be facilitated.
According to yet another aspect of the semiconductor device of the invention, the first internal clock generator generates an internal clock signal whose phase is inverted compared to the external clock signal. The second internal clock generator generates, by a delay circuit, a delayed internal clock signal which is delayed compared to the external clock signal. The clock generating unit outputs the inverted internal clock signal to the external clock signal, using the first clock generating unit, where the clock selecting signal is one signal level. The clock generating unit generates and outputs a delayed internal clock signal by the delay circuit of the second clock generating unit where the clock selecting signal is the other value. Therefore, for example, by changing the signal level of the clock selecting signal to the one or the other signal level according to a high or low level of the frequency of the external clock signal by means of, for example, the clock timing selecting unit, the input signal receiving unit receives an input signal by the inverted internal clock signal depending on the cycle of the external clock signal where the frequency of the external clock signal is high, and receives an input signal by a delayed internal clock signal that does not depend on the cycle of the external clock signal where the frequency of the external clock signal is low. That is, the input signal receiving unit is capable of accepting an input signal at the optimal and fastest timing in response to the frequency of the external clock signal.
According to yet another aspect of the semiconductor device of the invention, clock selecting information is provided in the selecting information setting unit. The clock timing selecting unit outputs a clock selecting signal according to the clock selecting information. Accordingly, it is possible to set clock selecting information in advance when operating a semiconductor device.
According to yet another aspect of the semiconductor device of the invention, a selecting information unit comprises a register that is able to be set from the exterior. The clock selecting information is set by accessing the register on a system equipment in which the semiconductor device is mounted, for example. The clock timing selection unit outputs a clock selecting signal having a signal level responsive to a storage value of the register. As the result, it is possible to set selecting information in response, to the frequency of the external clock signal in use when operating the semiconductor device, so that users are provided with a semiconductor device having a wide range of operating frequency.
According to still another aspect of the semiconductor device of the invention, the selecting information setting unit is composed of a fuse. The clock selecting information is set by whether or not the fuse in the test process blows. The clock timing selecting unit outputs a clock selecting signal of a signal level according to whether or not the fuse blows. Therefore, for example, the clock selecting information that is optimal for a produced semiconductor device can be set by blowing and not blowing the fuse in accordance with the maximum operating frequency evaluated in a probe test.
According to yet another aspect of the semiconductor device of the invention, the selecting information setting unit is composed of a bonding pad and bonding wire. The clock selecting information is set by changing the connection port of the bonding wire connected to the bonding pad in the assembly process. The clock timing selecting unit outputs a clock selecting signal of a signal level according to a voltage value given to the bonding wire connected to the bonding pad through the bonding wire.
According to yet another aspect of the semiconductor device of the invention, the selecting information setting unit is composed of a conductive layer formed at a predetermined position on a semiconductor substrate corresponding to the pattern of a photo mask. The clock selecting information is set by changing the photo mask used in a semiconductor fabrication process. The clock timing selecting unit outputs a clock selecting signal of a signal level corresponding to the voltage value at the connection port of the conductive layer. Since the clock selecting information is set in the photolithography process and etching process which are in the normal semiconductor fabrication process, the clock electing information is set without the provision of any special process.
According to yet another aspect of the semiconductor device of the invention, the clock timing selecting unit is provided with a frequency detector that detects the frequency of the external clock signal. The clock timing selecting unit automatically selects the internal clock signal according to the frequency of the detected external clock signal. Resultantly, in the semiconductor fabrication process, it is unnecessary to set the clock selecting information, or, it is unnecessary to set the clock selecting information to a system equipment having a semiconductor device mounted thereon.